Data acquisition devices are widely used in data processing, communication measurements, digital oscilloscopes and so on. In sampled data systems for those applications, when the sampling rate of the signal processing is high enough, it is not practical to process all samples of an input signal. In that situation, signal processing is generally restricted to segments of the input signal that are of interest for the specific application. Respective groups of samples are selectively positioned around reference points in the input signal, where reference points are determined by detection of particular “trigger events”. The groups of samples are initially loaded into an acquisition memory, followed by transfer to a signal processor.
A necessary component of a data acquisition device is an analog to digital converter (ADC). High speed acquisition requires the use of high speed multiple interleaved ADCs (sub-ADCs). To provide for high quality analog to digital conversion, misalignment in frequency responses of the individual sub-ADCs, and frequency distortions of the interleaved ADC as a whole, should be reduced to a minimum, which is achieved by the use of prior art digital equalization (see, for example, U.S. Pat. No. 7,408,495).
A prior art triggered acquisition device with digital equalization (as described, for instance, in US Patent Application Publication No. 2014/0047198) is typically built in accordance with the block diagram shown in FIG. 1. In that figure, an analog input signal is converted to a digital form by an analog to digital converter (ADC) 10. The digital signal from ADC 10 is applied to both an acquisition channel that consists of an acquisition memory 13 and a memory equalizer 14, and a trigger channel that consists of a trigger equalizer 11 and a trigger processor 12. An additional circuit is formed by a calibration unit 15 that consists of a frequency responses measurer 16 and a Fourier transform unit 17. In the block diagram of FIG. 1, the trigger equalizer 11 and trigger processor 12 operate in a real time (RT) mode, whereas the acquisition memory 13 and memory equalizer 14 operate in a not-real time (NRT) mode.
In the trigger channel, the function of the trigger processor 12 is to detect trigger events in the input signal. After a trigger event is detected, the trigger processor 12 produces at its output, corresponding signals that are applied to a control input of the acquisition memory 13. In the acquisition channel, the acquisition memory 13, managed by control signals coming from the trigger processor 12, stores a selected part of the input signal and then outputs that stored signal to be transferred to a processor that operates in a not-real time (NRT) mode.
The frequency responses measurer 16 of calibration unit 15 is responsive to the digital output of ADC 10 and performs measurements of the frequency responses of all individual sub-ADCs contained in interleaved ADC 10. The measured frequency responses, which are used as a basis for calculation of desired frequency responses of the equalizers 11 and 14, are transferred to the Fourier transform unit 17. Fourier transform unit 17 converts the desired frequency responses for the respective equalizers into sets of equalizer coefficients which are loaded into trigger equalizer 11 and memory equalizer 14 respectively.
In the trigger channel, the trigger equalizer 11 carries out equalization of the signal from ADC 10 and applies the equalized signal to the input of trigger processor 12. Trigger equalizer 11 corrects the misalignment in frequency responses of the individual sub-ADCs which are contained in the interleaved ADC 10, as well as the distortions in the frequency response of the ADC 10 as a whole. In a similar way, in the acquisition channel, the memory equalizer 14 corrects signal segments from acquisition memory 13, which are then transferred to an external NRT-mode processor. In this prior art system, the operations of the trigger equalizer 11 and the memory equalizer 14 are both computationally intensive, requiring significant system resources.
A prime consideration in the design of triggered acquisition devices with digital equalization, is given to the problem of reduction of required computation resources. Advances in this direction are hindered, in part, due to the fact that systems of the type illustrated in the block diagram of FIG. 1, possesses a certain redundancy: the trigger equalizer and the memory equalizer operate in parallel, and the equalization results achieved in one of the equalizers are not used in the other equalizer. This redundancy results in inefficiencies in operation, particularly in view of the computational complexity associated with the redundant computations and related processing.
The present technology substantially eliminates the redundancy exemplified in the system of FIG. 1, and similar prior art devices, and effects a significant reduction of required computation resources in a triggered acquisition device with digital equalization.